Embodiments of the present invention relate to a semiconductor device, and more particularly to a semiconductor device in which different voltages are applied to an upper buried gate overlapped with an ion implantation region according to a turn-on state or a turn-off state, and a method for manufacturing the same.
Recently, most electronic devices include at least one semiconductor device. Semiconductor devices include electronic elements such as transistors, resistors and capacitors that perform functions of the electronic appliances and are integrated on a semiconductor substrate. For example, an electronic appliance, such as a computer or a digital camera, may include a memory chip for storing information and a processing chip for controlling information. The memory chip and the processing chip include electronic elements integrated on a semiconductor substrate.
The degree of integration in semiconductor devices has been increasing in order to satisfy consumer demands for superior performance and low prices. An increase in the integration degree of a semiconductor device entails less tolerance in a design rule, thus requiring patterns of the semiconductor device to be significantly reduced. Although chip area is increased in proportion to an increase in memory capacity as the semiconductor device becomes miniaturized and more highly integrated, a unit cell area, where patterns of a semiconductor device are actually formed, decreases. Accordingly, since a greater number of patterns should be formed in a limited unit area in order to achieve a desired memory capacity, there is a need for formation of microscopic (fine) patterns having a reduced critical dimension (CD: a minimum pattern size available under a given condition).
Previously, various methods for forming microscopic patterns have been developed, including, for example, a method using a phase shift mask as a photo mask, a Contrast Enhancement Layer (CEL) method in which a separate thin film capable of enhancing image contrast is formed on a wafer, a Tri Layer Resist (TLR) method in which an intermediate layer, such as, for example, a Spin On Glass (SOG) film, is interposed between two photoresist films, and a silylation method for selectively implanting silicon into an upper part of a photoresist film.
Meanwhile, with the increasing integration of semiconductor devices, the length of a channel is reduced, so that high-density channel doping is necessary for transistor characteristics and to prevent deterioration of refresh characteristics. To accomplish this, there is a newly proposed technology for reducing bit line capacitance in which a recess gate structure is configured as a buried gate structure so that a gate is formed at a lower part of a bit line and both capacitance between the gate and the bit line and total capacitance of the bit line is reduced.
Generally, in the case of a buried gate, a semiconductor substrate is etched to a predetermined depth to form a trench, a gate metal is formed over the entirety of the substrate to bury the trench, and an etchback process is then performed on a gate electrode in such a manner that only the gate electrode of a predetermined thickness remains. In the etchback process, variation in the etched-back depth may occur.
When variation in the etched-back depth occurs, a junction region and a gate metal overlap with each other in response to a thickness of the remaining gate metal. In this case, gate induced drain leakage (GIDL) occurs so that a retention time of a cell is reduced, resulting in deterioration of the semiconductor device characteristics.